MAC/PHY loop-back diagnostic capability Supports 2 VLAN ID filtering, received VLAN Tag (4 bytes) can be stripped off or preserved Supports both Full-duplex with flow control and Half-duplex with backpressure operation Embedded 16KB SRAM for RX packet buffering and 8KB SRAM for TX packet buffering Supports twisted pair crossover detection and auto-correction (HP Auto-MDIX) ![]() Integrates 10/100Mbps Fast Ethernet MAC/PHY Supports USB to Ethernet bridging or vice versa in hardware High performance packet transfer rate over USB bus using proprietary burst transfer mechanism (US Patent Approval) Supports 4 or 6 programmable endpoints on USB interface Supports USB Full and High Speed modes with Bus-Power or Self-Power capability Integrates on-chip USB 2.0 transceiver and SIE compliant to USB Spec 1.1 and 2.0
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